Reconngurable Computing: Architectures, Models and Algorithms Current Science: Special Section on Computational Science

ion Mapping Parameters Scheduling Figure 2: Traditional Design Synthesis Approach and the Model-based Approach One major problem in using FPGAs to speed-up a computation is the design process. The \standard CAD approach" used for digital design is typically employed (see Figure 2). The required functionality is speci ed at a high level of abstraction via an HDL or a schematic. FPGA libraries speci c to a given device (e.g. Xilinx, Altera, etc.) and time consuming placement and routing steps are required to perform the logic mapping. This approach of logic synthesis as opposed to algorithm synthesis allows the user to specify the design using a behavioral model. But this abstraction is achieved at the expense of performance. The semantics and nature of the algorithm are lost in the mapping phases. The model based mapping environment takes into account the capabilities and limitations of current as well as projected hardware technologies. In Section 4 we illustrate some of the models and describe algorithmic approaches in Section 5. Parameterized models for algorithm design and analysis will possess the following characteristics: Cost models for analysis of recon gurable architectures. Techniques for partitioning and placement of designs exploiting algorithm and input structure. Cost analysis incorporating the cost of recon guration and partial and dynamic recon gurability. Impact of o -chip communication in designing recon gurable computing solutions. Tradeo s between recon gurability and redundancy of hardware. 5 Logic Configure Execute Execute Design Configurations Design Configurations Figure 3: Static con gurable computing Utilizing FPGAs for speeding-up applications has been mostly limited to developing con gurations which optimize the computation time for a given task. The optimized con guration is then used to execute the task. This process is illustrated in Figure 3. A given computational task is analyzed and an optimized con guration is developed for that computational task. The con gurable logic device is then con gured, usually under the control of the host, with this optimized con guration. Finally the con guration is executed by initiating the computation and communicating the data to the device. The programmability of the device is not exploited and the logic resources are not reused during a computation. Execute Design Configurations Design Logic Configure Configurations Execute Figure 4: Dynamic con gurable computing The conventional approach is static, because the hardware is con gured just once, followed by execution. The concept of dynamic con gurable computing is illustrated in Figure 4. The con gurable resources are reused by recon guring the hardware after a computation is completed. The con guration of the logic and the interconnection network are adapted on the y during the execution. The run-time recon guration can be based on intermediate results generated by the computations. This approach has enormous opportunities to achieve higher performance than conventional approach by closely adapting the hardware to the nature of the computation. 4 Recon gurable Computing Models Bridging the semantic gap between the algorithm and the hardware by using such a model allows the user to develop recon gurable computing solutions in a natural manner. We discuss here brie y a theoretical and a practical model which have been developed to map computations onto recon gurable architectures. 4.1 Recon gurable Mesh Model Recon gurable Mesh is a theoretical model of a VLSI array of processors overlaid with a recon gurable bus architecture [44, 45]. An overview of various models and architectures designed based on the model is given in [8]. A recon gurable bus architecture consists of a multi-dimensional array of processing elements (PEs) connected to a bus through a xed number of I/O ports. This bus architecture is capable, on a per instruction basis, of con guring a topology that contributes to solving the problem at hand. Bus recon guration is achieved by locally con guring the switches within each PE. Di erent shapes of buses such as rows, columns, diagonals, zig-zag, and staircase can be formed by con guring the switches/ports. 6 A two dimensional processor array with a recon gurable-bus system of size MN consisting of identical processors connected as a M N rectangular mesh system is called a recon gurable mesh. An example of a 4 4 recon gurable mesh is shown in Figure 5. A set of four I/O ports labeled N, E, W and S, connect each PE to its four neighbors to the north, east, west and south, respectively. Each PE has locally controllable switches which con gure the connection patterns between the four I/O ports. The switches allow the broadcast bus to be divided into sub-buses, providing smaller recon gurable meshes. The bus and all I/O ports are assumed to be m-bit wide. The connection patterns are represented as fg1,g2,...g, where each of gi represents a group of switches connected together. For example fNS,E,Wg represents the connection pattern with N and S connected and E and W unconnected. N Ε W S 0 1 2 3 0 1 2 3 PE(2,3) switch : Figure 5: Recon gurable Mesh. The basic computational unit of the recon gurable mesh is the Processing element (PE) which consists of a switch, local storage and an ALU (Fig. 5). In a unit time, a PE can perform: 1. Setting up of a connection pattern. 2. Read from or write onto a bus or local storage. 3. Logical or arithmetic operations on local data. Various models of recon gurable meshes have been proposed in the literature. Most of these models are synchronous in nature and permit unconditional global switch setting in addition to local switch control. Unconditional global switch setting is performed by the broadcast of a global instruction from a central controller. Recon gurable mesh models can be characterized by several parameters such as data width of the PE, signal propagation delay, shared/exclusive access to the bus, switch connection patterns, among others. 4.2 Hybrid System Architecture Model (HySAM) Hybrid System Architecture Model (HySAM) is a parameterized model of a con gurable computing system, which consists of con gurable logic attached to a traditional microprocessor. The HySAM model cleanly partitions the capabilities of the hardware from the implementations and presents a very clean interface to the user. Figure 6 shows the architecture of the HySAM model and an example of an architecture. The architecture consists of a traditional microprocessor, standard memory, con gurable logic, con guration memory and data bu ers communicating through an interconnection network. More details of the model can be found in [6, 9]. 7